1. Field of the Invention
The present invention relates to a manufacturing method for a transistor and particularly to a manufacturing method for a thin film transistor (TFT).
2. Descriptions of the Related Art
With development of the current technology, displays have been fabricated with an increasingly slighter weight and compacter volume. Although traditional cathode ray tubes have their advantages, they are heavy in volume and power consuming. In this regard, liquid crystal displays (LCDs), plasma displays and electroluminescence (EL) displays have become the mainstreamed displays on the market. Among them, the LCD is the most competitive since it provides the advantages of a lower operating voltage and being radiating ray free, slight in weight and small in volume.
In manufacturing of a LCD, a microphotography process is a critical and the most precision demanding step and costs the most, particularly an array process therein since numerous TFTs are required to be formed on a single substrate at same time. Therefore, reduction of step number in the manufacturing of the TFT may improve yield of the LCD and reduce cost therefor in efficiency.
FIG. 1A to FIG. 1G show sectional views of a TFT fabricated by a prior manufacturing method after each step is performed, respectively. Now referring to FIG. 1, a substrate 11 is first provided, which may be a glass substrate. Next, a first metal layer 12 is formed on the substrate 11. Then, a gate structure 12a is defined on the metal layer 12 by using a first photomask (not shown) and subsequently formed through an etching process. Referring to FIG. 1B, a first insulative layer 13 is formed on the gate structure 12a and the substrate 11. Referring to FIG. 1C, a semiconductor layer 15 is formed on the first insulative layer 13. Then, an n-type semiconductor layer 15a is formed on a surface of the semiconductor layer 15 through a doping process. Thereafter, a second photomask (not shown) is used to define a semiconductor structure 15b and then the semiconductor layer 15 and the n-type semiconductor layer 15a are etched to form the semiconductor 15b. Referring to FIG. 1D, a second metal layer 16 is formed on the semiconductor structure 15b and the first insulative layer 13. Then, a third photomask (not shown) is used to define a source structure 16a and a drain structure 16b and the second metal layer 16 is etched to form the source and drain structures 16a,16b. Referring to FIG. 1E, the third photomask is now taken as a mask to etch the n-type semiconductor layer 15a so as to form a channel structure 15c. Referring to FIG. 1F, a second insulative layer 17 is formed on the source and drain structures 16a, 16b, the channel structure 15c and the first insulative layer 13. Then, a fourth photomask (not shown) is used to define a contact window structure 17a and the second insulative layer 17 is etched to form the contact structure 17a. Referring to FIG. 1G, a transparent metal layer 18 is formed on the drain structure 16b and the second insulative layer 17. Then, a fifth photomask (not shown) is used to define a pixel electrode structure 18a and the transparent metal layer 18 is etched to form the pixel electrode structure 18a. 
Referring to FIG. 2, a flowchart illustrating a conventional manufacturing method for the TFT structure corresponding to FIG. 1A through FIG. 1G is shown therein. At first, provide a substrate having a gate structure with a first insulative layer formed on the gate structure and the substrate (S20), wherein the gate structure is formed by etching a first metal layer. Next, form a semiconductor layer and an n-type semiconductor layer on the first insulative layer (S21). Thereafter, form a first photoresist layer on the semiconductor layer and the n-type semiconductor layer (S22). Then, etch the semiconductor layer and the n-type semiconductor layer to form a semiconductor structure (S23). Next, remove the first photoresist layer (S24). Then, form a second metal layer on the semiconductor structure and the first insulative layer (S25). Thereafter, form a second photoresist layer on the second metal layer (S26). Subsequently, etch the second metal layer to form a source structure and a drain structure (S27). Then, etch the n-type semiconductor layer to form a channel structure (S28). Finally, remove the second photoresist layer (S29).
Since reduction of manufacturing step number may efficiently lead to a higher yield of the array manufacturing process and a lower cost therefor, the reduction issue is considered a very important matter in the LCD manufacturing field.